I do n’t quite understand the ARM pipeline recently. Which one can give an example?

king0k

Brother Beginner Heroes help

chiang999

Take ARM9TDMI as an example
He has 5 rapid pipelines, address decoding, ALU, load 1 and load 2
The next instruction requires the result of the previous instruction, and at this time the result has not yet come out, the processor will wait, which is called pipeline interlocking
Understand pulling the interlocking line is almost pulling
Example 1: No interlock
add r0, r0.r1
add r0, r0, r2
These two instructions take up to 2 cycles. ALU calculates r0 + r1 with 1 cycle, so this result is already well pulled by ALU calculation r0 + r2 in the second cycle

Example 2: A cycle interlock due to loading
ldr r1, [r2, # 4]
add r0, r0, r1
The two instructions are pulled for three cycles. The ALU calculates r2 + 4 in one cycle. The r1 used by add in the second cycle is not ready. Wait for one cycle, and the third cycle ldr has the result of r2 + 4. Load to r1, add can perform pull
Tired of typing

janeqin718

In fact, the problem of the pipeline need not be considered at all, after all, we did not design the CPU

chiang999

When the program is optimized, how much should be known

king0k

Seems to understand a little
Thank youchiang999janeqin718for two